1. Field of the Invention
The present invention relates generally to serial access semiconductor memory devices, and more particularly, to timing of serial data access among multiple memory array blocks. The invention has particular utility in the field of video memories (VRAMs).
2. Description of the Prior Art
Conventionally, an MOS memory (memory device having an MOS transistor as a component) has been used as a main storage of a computer. With recent development in semiconductor technology, a high-speed and large-capacity MOS memory has been achieved.
On the other hand, in recent years, an image signal has been digitally processed in the field of image processing, so that a high speed and large capacity memory capable of inputting and outputting pixel data at high speed has been required. A function required for a memory used in such a field of digital image processing comprises a high-speed serial access function. For example, when a video signal of an NTSC (National Television System Committee) system is sampled at 4 f.sub.sc (f.sub.sc is a chrominance subcarrier frequency; approximately 3.58 MHz), a video signal on a single horizontal scanning line is sampled into 256 pixel data. In a memory used for writing/reading such pixel data, a cycle time for one pixel must be 69.8 ns or less. In addition, if consideration is given to the uses such as non-interlace conversion (the video signal on the horizontal scanning line in video signals applied in an interlace manner is continuously read out two times, to be converted into a non-interlaced video signal), a cycle time of approximately 30 ns is required for a sampling frequency 8f.sub.sc.
In order to operate the MOS memory at such high speed, an approach has been conventionally used of frequency-dividing an external clock (obtained by multiplying a chrominance subcarrier if a video signal is digitally processed, for example to produce an internal clock, operating internal circuits in the memory by the frequency-divided clock in a time-divisional manner, respectively, and thus substantially decreasing an operation frequency of the memory.
FIG. 8 is a diagram showing schematically the entire structure of the conventional memory capable of performing a serial access operation.
In FIG. 8, a memory cell array storing information is divided into two array blocks 10 and 11 by way of example. Each of the memory cell array blocks 10 and 11 has a plurality of memory cells arranged in rows and columns.
In order to write/read data to/from the memory cell array block 10, there are provided a shift register 20 receiving and sending data from and to memory cells on a selected one row in the memory cell array block 10, a data-in buffer 30 responsive to a clock signal .phi..sub.O to be activated for serially transmitting input data to the shift register 20, and a data-out buffer 40 responsive to the clock signal .phi..sub.O to be activated for serially reading out data latched in the shift register 20. The shift register 20 has data latching and shifting functions, which performs a data shifting operation in response to the clock signal .phi..sub.O. In addition, the shift register 20 is connected to either one of the data-in buffer 30 and the data-out buffer 40 in response to a control signal (read/write enabling signal) W.
In order to write/read data to/from the memory cell array block 11, there are provided a shift register 21 receiving and sending data from and to memory cells on a selected one row in the memory cell array block 11, a data-in buffer 31 responsive to a clock signal .phi..sub.1 to be activated for transferring write data to the shift register 21 in series, and a data-out buffer 41 responsive to the clock signal .phi..sub.1 to be activated for serially reading out data latched in the shift register 21. The shift register 21 has data latching and shifting functions, timings for data shifting operation thereof being provided by the clock signal .phi..sub.1. In addition, the shift register 21 is connected to either one of the data-in buffer 31 and the data-out buffer 41 in response to the control signal W.
In order to select respective one rows in the memory cell array blocks 10 and 11, there are provided a timing generator 60 responsive to a control signal RAS externally applied for generating an operation timing signal, an address counter 61 responsive to a timing signal from the timing generator 60 for incrementing or decrementing a count value thereof, an X decoder 62 for decoding information from the address counter 61 to select memory cells on one row in the memory cell array block 10, and an X decoder 63 for decoding address information from the address counter 61 to select memory cells on one row in the memory cell array block 11.
In addition to the above described structure, in order to generate various control signals, there is provided a control signal generator 100 responsive to an external clock signal .phi. and a signal SE for enabling a serial access system for generating clock signals .phi..sub.O and .phi..sub.1, a control signal W and the like.
In the above described structure, when the serial access system is enabled, the same address information is applied to the memory cell array blocks 10 and 11, so that data is written/read out from/to memory cells connected to one row in the memory as a whole.
FIG. 9 is a diagram showing one example of a more specific structure of the shift register block shown in FIG. 8.
In FIG. 9, the shift register comprises a transfer gate TG comprising transfer transistors Ql to Qn respectively provided corresponding to bit lines BLl to BLn in a memory cell array MA, a data latch DT receiving and sending information from and to memory cells MC connected to a selected word line WL in the memory cell array MA through the transfer gate TG, a shift selector SS responsive to a clock signal .phi..sub.O (or .phi..sub.1) for shifting a 1-bit "H" level signal to output the same, a select gate SG responsive to a signal from the shift selector SS for sequentially connecting a 1-bit latch portion in the data latch DT to an input/output line I/0, a switching transistor Gl responsive to a write/read enable signal W to be rendered conductive for connecting the data input/output line I/0 to a data-in buffer, a switching transistor G2 responsive to the write/read enable signal W to be rendered conductive for connecting the data input/output line I/0 to a data-out buffer. The select gate SG comprises switching transistors T1, T2, . . ., Tn provided correspondingly to latch portions in the data latch DT. Timings for data transfer of the transfer gate TG are provided by a control signal TE.
In the above described structure, data is serially inputted and outputted to and from the data latch DT in response to a clock signal .phi..sub.O (or .phi..sub.1). In addition, data transfer between the data latch DT and the memory cell array MA is collectively and simultaneously made to a single word line WL.
FIG. 10 is a diagram showing another example of the structure of the shift register shown in FIG. 8, which comprises a shift register SR responsive to a clock signal CLK (.phi..sub.O or .phi..sub.1) for performing a data shifting operation as well as a data latching operation, a transfer gate TG responsive to a control signal TE for connecting the shift register SR to a selected word line in a memory cell array MA, a switching transistor Gl responsive to a write/read enable signal W to be rendered conductive for connecting the shift register SR to a data-in buffer, and a switching transistor G2 responsive to the write/read enable signal W to be rendered conductive for connecting the shift register SR to a data-out buffer. In the structure shown in FIG. 10, at the time of writing data, data is first transferred serially to the shift register SR from the data-in buffer through the shifting transistor Gl in response to the clock signal CLK. The data latched in the shift register SR are then written to memory cells on a selected one row in the memory cell array MA through the respective corresponding transfer gate TG under control of the control signal TE. At the time of data reading, data in the memory cells on a selected one row are collectively transferred to the shift register SR through the transfer gate TG and then, the data are outputted in series from the shift register SR through the switching transistor G2 and the data-out buffer under control of the clock signal CLK.
FIG. 11 is a diagram showing one example of a structure of the shift register SR and the shift selector SS as shown in FIGS. 9 and 10. In FIG. 11, a block having a shifting function comprises the same number of unit latches USRl to USRn as the number of bit line (memory cells) connected to a word line of one row. Each of the unit registers comprises two inverters I1 and I2 connected in series and a transistor switch Q2 provided between the inverters I1 and I2. Each of an input portion and an output portion of the unit register is provided with a transistor switch Ql for shifting data. The transistor switch Ql is responsive to a clock signal CLK to be rendered conductive for performing a data shifting operation. The transistor switch Q2 in the unit register is responsive to a clock signal CLK to be rendered conductive for performing a data latching operation.
Internal clock signals .phi..sub.O and .phi..sub.1 are applied by frequency-dividing a clock signal .phi. externally applied or by a gating processing thereon.
FIG. 12 is a waveform diagram of signals showing a data reading operation of a memory serially accessible shown in FIG. 8. Referring now to FIGS. 8 and 12, the data reading operation will be described.
First, when the externally applied signal SE for activating the serial access system enters an active state (attains "H" level in FIG. 12), the internal clock signals .phi..sub.O and .phi..sub.1 and the read enable signal W are issued from the control signal generator 100. At the time of data reading, the write/read enabling signal W is set to an "L" level indicating a reading operation. The internal clocks .phi..sub.O and .phi..sub.1 are applied by frequency-dividing the clock signal .phi. externally applied. The clock signal .phi..sub.O is generated in synchronization with clock pulses in odd numbers of the external clock signal .phi., and the internal clock signal .phi..sub.1 is generated in synchronization with clock pulses in even numbers of the external clock signal .phi.. On this occasion, the shift registers 20 and 21 are connected to the data-out buffers 40 and 41 in response to the write/read enabling signal W, respectively. After data in the memory cells connected to the respective selected word lines in the memory cell array blocks 10 and 11 are respectively transferred to the shift register 20 and 21, the data latched in the shift register 20 is read out through the data-out buffer 40 in response to the clock signal .phi..sub.O while the data latched in the shift register 21 is read out through the data-out buffer 41 in response to the clock signal .phi..sub.1. Since the respective shifting operations in the shift registers 20 and 21 are alternately performed and the data-out buffers 40 and 41 are alternately activated, the data read out from the memory cell array blocks 10 and 11 are alternately and sequentially read out in series from the data-out buffers 40 and 41. Consequently, data can be read out in response to a high-speed external clock signal .phi. with internal circuitry operating at half a frequency of the external clock signal .phi..
In the above described structure, an X address for selecting memory cells on one row from each of the memory cell array blocks 10 and 11 is generated from the address counter 61 in response to the timing signal from the timing generator 60 which is activated in response to the signal RAS. Address information from the address counter 61 is applied to the X decoders 62 and 63, so that memory cells on one row are selected from each of the memory cell array blocks 10 and 11. Respective data transfers between the memory cell array blocks 10 and 11 and the shift registers 20 and 21 are made through the transfer gate TG as previously described with reference to FIGS. 9 and 10. The control signal TE is responsive to the timing signal from the timing generator 60 and the enabling signal SE for a serial access system to be generated after the word line is selected (the details of this structure are not shown).
FIG. 13 is a waveform diagram showing a data writing operation of the serial access memory shown in FIG. 8. Referring now to FIGS. 8 and 13, the data writing operation will be described. First, the serial access operation is performed in response to the rise to the "H" level of the control signal SE externally applied. In response thereto, the "H" level write enabling signal W is generated from the control signal generator 100, to be applied to the shift registers 20 and 21. Consequently, the shift register 20 and 21 are connected to the data-in buffers 30 and 31, respectively. Then, data are serially transferred to the shift registers 20 and 21 through the data-in buffers 30 and 31 in response to the internal clock signals .phi..sub.1 and .phi..sub.O produced by frequency-dividing the external clock .phi.. More specifically, the data-in buffer 30 first serially transfers data in odd numbers in a data stream to the shift register 20 in response to the clock signal .phi..sub.O, and the data-in buffer 31 transfers data in even numbers in a data stream to the shift register 21 in response to the clock signal .phi..sub.1. After the data are transferred to the shift registers 20 and 21, the data latched in the shift registers 20 and 21 are transferred into memory cells connected to the respective selected word lines in the memory cell array blocks 10 and 11, so that a data writing operation is performed.
As described in the foregoing, in the serial access operation, a word line has been selected in the memory cell array simultaneously or in parallel with data transfer to the shift registers at the time of data writing. Data are written to the memory cells connected to the selected word line after the operation of transferring data to the shift registers is completed. In addition, at the time of data reading, data from the selected word line can be collectively transferred at a time to the shift registers, to be serially output from the shift registers and the next word line is selected simultaneously with data output to prepare for the next data reading operation. Therefore, a data writing/reading operation can be performed at higher speed, as compared with the conventional bit-by-bit operation or page mode operation. The page mode is an operation mode where while the signal RAS is maintained at "L" level, the signal CAS is toggled to accept a column address to select a column out of the memory cell array each toggle of the signal CAS. That is, one page data selected by a row address is selected sequentially by a column address strobed at each toggling of the signal CAS. However, in the above described structure, internal clock signals respectively applied to a portion associated with the memory cell array block 10, the shift register 20, the data-in buffer 30 and the data-out buffer 40 and to a portion associated with the memory cell array block 11, the shift register 21, the data-in buffer 31 and the data-out buffer 41 are different from each other by one cycle of the high-speed external clock signal .phi.. Thus, if and when the memory cell array is divided into the blocks and each of the blocks is operated in a time-divisional manner, as described above, respective circuitry related to the blocks must be operated at different operation timings corresponding to the respective internal clock signals. However, in this case, the operation timings for the blocks differ from each other by one cycle of the external clock. Since the external clock is fast, i.e. 4f.sub.sc or 8f.sub.sc as described above, the design of the operation timings for the entire memory becomes substantially difficult. In addition to the difficulty of the timing design (design of timings for each circuitry), a problem is caused when each of the shift register blocks is operated in a time-divisional manner using the above described internal clock signals having different phases, the following problem occurs: operations of a latching transistors and a transferring transistors included in a shift register block must be controlled by the same clock signal. However, if and when the number of bit lines (memory cells) connected to a single word line is increased, the number of switching transistors (latching transistors and transferring transistors) is responsively increased. Similarly, the number and the length of signal lines for transmitting the clock signals thereto are increased, so that delay in signal transmission due to a long interconnection occurs. In order to avoid this delay and operate a lot of latching transistors and transferring transistors in synchronization with each other using the same clock signal, the driving capability of a clock signal generating circuit must be increased, so that the size of the clock signal generating circuit is increased, which causes a large difficulty against high integration density. Furthermore, if the shift register comprising a lot of register portions is operated in response to a clock signal, an interconnection becomes long, so that the layout of the interconnection becomes complicated, which causes a difficulty on the circuit design.
As an example, considered is a serial access memory in which one row of the memory cell array is provided with 1024 memory cells. In this memory, each shift register should have 1024 stages of unit registers. Thus, a clock signal line for transferring a clock for driving the shift register becomes long to provide a large capacitance, resulting in a clock transferring delay. In such circumstances, if non-overlapping clocks are employed for driving the two separate shift registers, some unit registers in respective shift registers operates in an overlapping manner to provide erroneous data transfer. In addition, two separate clock signal lines should be provided for the two separate shift registers to require a large area for the interconnection of the clock lines between the shift registers and the shift register drivers. Further, in the conventional device, two shift register drivers are provided for driving the shift registers to occupy a large area in a device chip. Still further, two long clock lines are provided in the regions near to each other to cause interference of the shift clocks between the two clock lines, so that the shift registers cannot operate at a sufficiently correct timing for the memory blocks to operate in a time-divisional manner.
Thus, if and when the memory cell array must be divided into a plurality of blocks and the internal circuits must be independently operated in a time-divisional manner corresponding to the blocks, the blocks are independently operated in a time-divisional manner by the internal clock signals, so that problems such as the difficulty in the above described timing design occur.